This patent application claims priority based on Japanese patent applications, H10-308430 filed on Oct. 29, 1998, H10-137082 filed on May 19, 1998, and H10-174218 filed on Jun. 22, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing a semiconductor device (also called xe2x80x9cDUTxe2x80x9d. For example, semiconductor integrated circuit or the like), and more particularly to a calibration jig of the semiconductor device testing apparatus and a method for calibrating the semiconductor device testing apparatus.
2. Description of Related Art
FIG. 1 is a cross sectional view of a conventional semiconductor testing apparatus. The test head 70 outputs a test signal for testing the semiconductor device 20 and receives an output signal output from the semiconductor device 20. A performance board 66, which transmits signals to the test head 70 through the coaxial cables 62 and 64, is installed on the test head 70. The coaxial cable 62 transmits the test signal from the performance board 66 to the socket board 60. The coaxial cable 62 also transmits the output signal from the socket board 60 to the performance board 66. A socket 50 is installed on the socket board 60. The test signal is supplied to the semiconductor device 20 through the pin 52 and the first terminal 12 of the socket 50. The output signal is received from the semiconductor device 20 via the second terminal 14 and the pin 54.
The test head 70 has a driver 76 (76A and 76B) for generating test signals, drive delay circuits 78 (78A and 78B) for delaying the test signals generated by the drivers 76, comparators 80 (80A and 80B) for receiving the output signal, and comparator delay circuits 82 (82A and.82B) for delaying the time at which the comparators 80 output the output signal after the comparators 80 have received the output signal. The test signal output from each of the drivers 76 is measured using a measuring apparatus such as an oscilloscope. The delay times given by the driver delay circuits 78 are adjusted so that the output timings at which the test signals are output from the drivers will be equal to each other. Thus, the skews between the drivers 76 can be canceled by each other. Moreover, by adjusting the delay times given by the comparator delay circuits 82, the skews between the comparators 80 can be canceled by each other.
FIG. 2(a) is a top view of the semiconductor device 20. FIG. 2(b) is a front view of the semiconductor device 20. The semiconductor device 20 shown here is of TSOP type. However, the semiconductor device 20 may be of QFP or BGA type. Semiconductor devices of different types can be tested by preparing a socket 50 for each of the different semiconductor device types. The semiconductor device 20 has a semiconductor device input pin 22 for inputting a signal and a semiconductor device output pin 24 for outputting a signal. These pins contact the first terminal 12 and second terminal 14, respectively.
FIG. 3 is a cross sectional view of the socket 50 and the socket board 60 on which the socket 50 is mounted. When the socket 50 is installed on the socket board 60 along the socket guide 58 of the socket board 60, the pins 52 and 54 of the socket 50 are inserted into the corresponding through holes 56 of the socket board 60. Moreover, the core wires of the coaxial cables 62 and 64 are inserted into and soldered to the corresponding through holes 59 from the bottom side. In recent years, the number of pins used in the semiconductor device has increased. Hence, it is getting difficult to bring the probe of an oscilloscope or the like into contact with the first terminal 12 of the socket 50 accurately. A method for solving this problem is being proposed, in which the socket 50 is removed from the semiconductor device 20 and the probe is brought into direct contact with the socket board.
FIG. 4 is a top view of the socket board 60. Installed on the socket board 60 are through-holes 56 for inserting the pins 52 and 54 of the socket 50 and through-holes 59 for inserting and soldering the coaxial cables 62 and 64. Moreover, an earth pattern (GND) and a power source pattern (VDD) are installed on the top surface of the socket board 60. By bringing the probe of the oscilloscope into contact with the socket board 60, the semiconductor testing apparatus can be calibrated.
FIG. 5 shows a state in which the probe 44 is in contact with the socket board 60. The probe 44 has a signal terminal 40 and an earth terminal 42. The socket 50 is first removed from the socket board installed on the testing apparatus. The signal terminal 40 of the probe 44 is then brought into contact with the socket through-hole 56. The earth terminal 42 is then brought into contact with the earth pattern on the socket board 60. In this way, a signal supplied to the through-hole 56 is measured. However, when the earth pattern is not near the through-hole to be measured, the earth-line of the probe 44 connected to the earth terminal 42 must be made long. In this case, the line impedance during the measurement becomes large. In recent years, as the semiconductor device 20 becomes faster, the semiconductor device 20 needs to be tested with a higher degree of accuracy. Therefore, the semiconductor testing apparatus also needs to be calibrated with a higher degree of accuracy. However, when the line impedance is large when the test signal is measured, the semiconductor testing apparatus cannot be calibrated accurately.
The signal wire pattern and the earth pattern are installed adjacent to each other on the performance board 66. Hence, the line impedance of the signal can be reduced by removing the socket 50, the socket board 60, and the coaxial cables 62 and 64, and bringing the probe into direct contact with the performance board 66. However in this case, the influence of the inductance and floating capacitance of the socket 50, socket board 60, and coaxial cables 62 and 64 do not appear on the test signal. Therefore, the semiconductor testing apparatus cannot be calibrated accurately in the actual testing state.
FIG. 6 shows another conventional method for calibrating the semiconductor testing apparatus. In this embodiment, a comparator 80 and a programmable load 180 are installed parallel with the driver 76. By setting the programmable load 180 suitably, a load of desired level can be applied to the driver 76. The semiconductor device 20 is removed from the socket 50, and a test signal is output from the driver 76. The test signal then is reflected by the top end of the socket 50 and is input to the comparator 80. By dividing by 2 the time t1 required for the test signal to travel from the drive 76 to the comparator 80 via the top end of the socket 50, the signal transmission time from the drive 76 to the socket 50 can be measured.
FIG. 7 shows further another embodiment of the conventional semiconductor testing apparatus. As shown in FIG. 7, two coaxial cables are connected to each pin of the socket 50. In this case, even if a test signal is generated after removing the semiconductor device 20, the test signal is transmitted to the comparator 90 without being reflected by the socket 50. Hence, the test signal transmission time from the drive 76 to the socket 50 cannot be measured.
FIG. 8 is a flow chart showing a conventional calibration method. First, the probe 44 is brought into contact with the through-hole 56 of the socket board 60 and the earth pattern GND, which are the points of measurement (S302). Next, timing measurement and calibration are carried out (S310). That is, the timing at which the wave form of the test signal output from a 1-channel driver rises or falls is measured to obtain calibration data. Next, the setting value of the driver delay circuit 78 is set to the initial condition, and a test signal is generated under a prescribed amplitude condition (S312). Next, the timing of the rise of the wave form of the test signal is measured, and the driver 76 is calibrated along with the rising wave form (S314). Next, the timing of the falling wave form of the test signal is measured, and the driver 76 is calibrated along with the falling wave form (S316).
FIG. 9(a) shows the wave form of the test signal measured in the timing measuring S310. The wave form S0 is at 50% level at the reference timing position t0. The wave form S1 is at 50% level at the reference timing position t1. The wave form S2 is at 50% level at the reference timing position t2. The slew rate is represented by the slope of the rise or fall of the wave form. The multiple drivers 76 of the test head 70 are adjusted so that they will output signals with the slew rate of 500 pico seconds/Vxc2x1(less than 10%). In the rising wave form measuring S314, as shown in FIG. 9(b), the delay amount of each of the driver delay circuits 78 that correspond to the multiple drivers 76 is adjusted to shift the timings t1 and t2 to t0. In this way, the multiple drivers 76 are calibrated. As a result of this shift, the setting data in which the delay amounts of the driver delay circuits 78 are increased or decreased is obtained as calibration data. When the resistance values of the signal terminal 40 of the probe 44 and the through hole 56 of the socket board 60 are high due to a dust or the like, the signal level of the test signal becomes lower than 50%. In such a case, it can be easily determined that a contact failure exists.
FIG. 9(c) shows the wave form of the test signal in the case in which a contact failure exists between the earth terminal 42 of the probe 44 and the earth pattern GND. The wave form S4 is an exemplary wave form when the earth terminal 42 of the probe 44 and the earth pattern GND are open. The wave form S6 is an exemplary wave form when there is a high contact resistance between the earth terminal 42 of the probe 44 and the earth pattern GND. The wave forms S4 and S6 are rounded and distorted. However, the 50% level is measured for both the wave forms S4 and S6 as in the case of the normal wave form S0. In this case, when the calibration is carried out, the contact failure is overlooked. Since the calibration cannot be carried out at the proper timing position, there is a possibility that a wrong calibration is performed. For example, in the wave form S6, there is a timing displacement e2 with respect to the normal wave-form S0. Moreover, also in the wave form S4, there is a timing displacement e1 with respect to the normal wave form S0. Hence, the drivers 76 are calibrated at a wrong timing. When the calibration is carried out in the presence of a timing displacement, the calibration accuracy or the reliability of the calibration operation deteriorates.
As a method for checking a contact failure, the method of measuring the direct current resistance at the contact point between the robe 44 and the socket board 60 is known. This method can be used to detect a contact failure between the signal terminal 40 of the probe 44 and the through hole 56 of the socket board 60. However, a contact failure between the earth terminal 42 of the probe 44 and the earth pattern GND of the socket board 60 that is a ground side line is difficult to detect since the earth pattern GND is a circuit earth and is commonly connected.
It is an object of the present invention to provide a semiconductor testing apparatus capable of solving at least one of the above-stated problems. The object of the present invention can be achieved by a combination of characteristics described in the independent claims of the present invention. Moreover, the dependent claims of the present invention determine further advantageous embodiments of the present invention.
According to the first aspect of the present invention, A calibration method for calibrating an output timing of a test signal of a semiconductor testing apparatus is provided. The semiconductor testing apparatus has a socket on which a semiconductor device is mounted, the socket having a first terminal capable of supplying the test signal to be used to test the semiconductor device and a driver which outputs the test signal to the first terminal can be provided. This calibration method has mounting onto the socket a test board having a pin arrangement corresponding to a pin arrangement of the semiconductor device, generating the test signal using the driver, detecting the test signal that has reached the test board, setting an output timing of the test signal based on the test signal detected in the test signal detecting.
According to the other aspect of the present invention, a calibration method can be provided such that a pin of the test board that contacts the first terminal has an input impedance that is substantially equal to an input impedance of a pin of the semiconductor device that contacts the first terminal.
According to the still other aspect of the present invention, a calibration method can be provided such that a contact terminal of the test board that contacts the first terminal is connected to an earth pattern of the test board, and wherein the detecting includes measuring the test signal that has been output from the driver and reflected by the test board.
A calibration method can be provided such that the mounting includes examining a contact failure between the socket and the test board by measuring a direct current resistance between the socket and the test board.
A calibration method can be provided such that the semiconductor testing apparatus further has a comparator which receives the test signal from the test board. The mounting has measuring the test signal that has been output from the driver and reflected by the test board using the comparator, judging whether a wave form of the test signal measured by the comparator lies within a prescribed range or not, and reporting a contact failure on a transmission line between an output end of the driver and the test board when the wave form measured by the comparator lies outside the prescribed range.
A calibration method can be provided such that the semiconductor testing apparatus further has a delay circuit which supplies a delay to the test signal. The generating includes outputting the test signal using the driver and generating a prescribed reference signal. The setting has a delay setting for setting a size of the delay supplied to the test signal detected in the test signal detecting by the delay circuit based on a phase difference with respect to the reference signal.
A calibration method can be provided such that the test board has a signal wire pattern for contacting the first terminal and an earth pattern that is arranged adjacent to the signal wire pattern. The detecting includes detecting the test signal using an electric characteristic testing probe installed on the earth pattern and the signal wire pattern.
A calibration method can be provided such that the mounting includes examining a contact failure by measuring a direct current resistance between the electric characteristic testing probe and the test board.
A calibration method can be provided such that the mounting has checking a contact failure between the electric characteristic testing probe and the test board. The checking includes contacting the electric characteristic test probe with the test board, measuring in an external measuring apparatus the test signal detected by the electric characteristic test probe, judging whether a wave form of the test signal measured by the external measuring apparatus lies within a prescribed range, and reporting a contact failure between the electric characteristic test probe and the test board when the wave form measured by the external measuring apparatus lies outside the prescribed range.
A calibration method can be provided such that the socket further has a second terminal which contacts the semiconductor device and receives an electric signal from the semiconductor device. The semiconductor testing apparatus further has a comparator for receiving a signal input from the second terminal. The test board is a short board including a short pattern which electrically connects the first terminal with the second terminal.
A calibration method can be provided such that the detecting has detecting the test signal that has been output from the driver and passed through the short board by the comparator, and setting, as a reference time for testing the semiconductor device for the comparator, a value obtained based on a time difference between a reference timing having a prescribed time difference with respect to the generating and a time at which the test signal is detected in the detecting.
According to the still other aspect of the present invention, a calibration method for calibrating a processing timing of a semiconductor testing apparatus can be provided such that the semiconductor testing apparatus has a socket including a first terminal capable of supplying a test signal to the semiconductor device when a semiconductor device is mounted on the semiconductor testing apparatus, and a second terminal which receives an electric signal from the semiconductor device, a driver which outputs the test signal to the first terminal, and a comparator which receives a signal from the second terminal. This calibration method has mounting onto the socket a short board having a short pattern which electrically connects the first terminal with the second terminal, outputting the test signal from the driver, measuring in the comparator the test signal that has been output from the driver and passed through the short board, and setting, as a reference time that is used to test the semiconductor device for the comparator, a value obtained based on a time difference between a reference timing having a prescribed time difference with respect to the test signal outputting and a time at which the test signal is measured in the test signal measuring.
A calibration method can be provided such that the semiconductor testing apparatus has a plurality of the drivers and a plurality of the comparators. The socket has a plurality of the first terminals corresponding to the plurality of the drivers and a plurality of the second terminals corresponding to the plurality of the comparators, and the short board has a plurality of the short patterns which connect the plurality of the first terminals with the second terminals, respectively. In the setting, the reference time is set for each of the plurality of the comparators independently of each other.
According to the still other aspect of the present invention, a calibration method for calibrating a processing timing of a semiconductor testing apparatus can be provided such that the semiconductor testing apparatus has a driver which outputs a test signal for testing a semiconductor device, a comparator which receives an electric signal from the semiconductor device, a socket capable of supplying the test signal to the semiconductor device when the semiconductor device is mounted on the semiconductor testing apparatus. The calibration method has a providing a desired connection to a measuring apparatus which measures a wave form of the test signal so as to supply the test signal or the electric signal, measuring in the measuring apparatus the test signal output from the driver, judging whether a wave form of the test signal measured by the measuring apparatus lies within a prescribed range or not, reporting that a connection made to the measuring apparatus is a failure when the wave form measured by the measuring apparatus lies outside the prescribed range.
A calibration method can be provided such that a rising wave form or falling wave form of the test signal is measured in the measuring.
A calibration method can be provided such that the reporting has repeating the connecting, the wave form measuring, and the wave form judging when the wave form lies outside the prescribed range, and reporting that the connection made to the measuring apparatus is a failure when the wave form lies outside the prescribed range after the providing, the measuring, and the judging have been repeated by a prescribed number of times.
A calibration method can be provided such that the measuring apparatus is installed outside the semiconductor testing apparatus, and the measuring apparatus has an electric characteristic test probe for inputting the test signal. The providing includes carrying out a necessary connection so as to supply the test signal to the an electric characteristic test probe.
A calibration method can be provided such that the measuring apparatus is installed inside the semiconductor testing apparatus, and the measuring includes measuring in the measuring apparatus the test signal, which has been output from the driver, reflected by the socket, and input from the comparator.
A calibration method can be provided such that the measuring apparatus is installed inside of the semiconductor testing apparatus, and the measuring includes measuring in the measuring apparatus a prescribed reference signal that has been input from the comparator.
A calibration method can be provided such that the providing includes connecting a test board, which inputs the test signal and provides the test signal to the measurement apparatus, with the measurement apparatus for the calibration.
A calibration method can be provided such that the measuring apparatus is installed inside the semiconductor testing apparatus, and the measuring includes measuring in the measuring apparatus the test signal, which has been output from the driver, reflected by the test board, and input from the comparator.
A calibration method can be provided such that the judging judges whether a level of the test signal during a rising or falling of the test signal lies within a prescribed range or not.
According to the still other aspect of the present. invention, a semiconductor testing apparatus for testing an electric characteristic of a semiconductor device is provided. The semiconductor testing apparatus has a socket having a first terminal which contacts the semiconductor device and supplies a signal to the semiconductor device, a test board, which has a pin arrangement identical to a pin arrangement of the semiconductor device, capable of being mounted onto the socket, a driver which outputs a test signal to the first terminal, and an output timing setting unit for setting an output timing at which the driver outputs the test signal using the test signal that has been output from the driver and reached the test board.
A semiconductor testing apparatus can be provided such that the test board has a signal wire pattern for contacting the first terminal and an earth pattern that is arranged adjacent to the signal wire pattern.
A semiconductor testing apparatus can be provided such that the test board has a signal wire pattern for contacting the first terminal and connecting the first terminal to earth, and the output timing setting unit sets the output timing using the test signal that has been output from the outputting unit and reflected by the test board.
A semiconductor testing apparatus can be provided such that the test board has a test pin that contacts the first terminal and has an input impedance that is equal to an input impedance of a pin of the semiconductor device.
A semiconductor testing apparatus can be provided such that the semi conductor testing apparatus further has a delay circuit which supplies a desired delay to the test signal, the output timing setting unit having a generating unit for outputting the test signal and generating a prescribed reference signal, and the output timing setting unit which sets the output timing by setting a size of a delay supplied by the delay circuit.
A semiconductor testing apparatus can be provided such that the semiconductor testing apparatus further has a plurality of the drivers and a plurality of delay circuits corresponding to the plurality of the divers, and the socket having a plurality of the first terminals corresponding to each of the plurality of the drivers, and the test board having a plurality of signal wire patterns corresponding to each of the plurality of the first terminals.
A semiconductor testing apparatus can be provided such that shortest distances between the plurality of the signal wire patterns and the earth pattern are substantially same.
A semiconductor testing apparatus can be provided such that the socket further has a second terminal which contacts the semiconductor device and receives an electric signal from the semiconductor device. The semiconductor testing apparatus further has a short board including a short pattern which electrically connects the first terminal with the second terminal and a comparator for measuring the test signal that has been output from the driver and passed through the short board.
A semiconductor testing apparatus can be provided such that the semiconductor testing apparatus further has a reference time setting unit for setting, as a reference time that is used to test the semiconductor device for the comparator, a value obtained based on a time from a reference timing having a prescribed time difference with respect to the test signal output to a time at which the test signal is measured in the comparator.
A semiconductor testing apparatus can be provided such that the semiconductor testing apparatus has a plurality of the drivers and a plurality of the comparators, the socket that has a plurality of the first terminals corresponding to the plurality of the drivers and a plurality of the second terminals corresponding to the plurality of the comparators, and the short board that has a plurality of the short patterns which connect the plurality of the first terminals with the second terminals, respectively. In the reference time setting unit, the reference time is set for each of the plurality of the comparators independently of each other.
A semiconductor testing apparatus can be provided such that the semiconductor testing apparatus further has a plurality of the sockets, a plurality of the test boards corresponding to each of a plurality of the sockets, a frame which holds a plurality of the test boards, and the frame having a take-in structure to shift the test boards to desired positions when mounting the frame at prescribed position on the semiconductor testing device.
According to the still other aspect of the present invention, a semiconductor testing apparatus for testing an electric characteristic of a semiconductor device can be provided. The semiconductor testing apparatus has a socket having a first terminal which contacts the semiconductor device and supplies an electric signal to the semiconductor device and a second terminal which contacts the semiconductor device and receives an electric signal from the semiconductor device, a driver which outputs a test signal to the first terminal, a short board which electrically connects the first terminal to the second terminal, a comparator which receives a signal input from the second terminal, a test signal detecting unit which detects in the comparator the test signal that has been output from the driver and passed through the short board, and a reference time setting unit for setting, as a reference time for testing the semiconductor device for the comparator, a value obtained based on a time difference between a reference timing having a prescribed time difference with respect to an output of the test signal output by the driver and a time at which the comparator has detected the test signal.
A semiconductor testing apparatus can be provided such that the semiconductor testing apparatus has a plurality of the drivers and a plurality of the comparators, the socket has a plurality of the first terminals corresponding to the plurality of the drivers and a plurality of the second terminals corresponding to the plurality of the comparators, and the short board has a plurality of signal wire patterns which connect the plurality of the first terminals with the second terminals, respectively. In the reference time setting unit, the reference time is set for each of the plurality of the comparators independently of each other.
A semiconductor testing apparatus can be provide such that the semiconductor testing apparatus further has a plurality of the sockets, a plurality of the short boards corresponding to each of a plurality of the sockets, a frame which holds a plurality of the short boards, and the frame having a take-in structure to shift the short boards to desired positions when mounting the frame on prescribed position.